Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
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Communications of the ACM
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FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
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TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
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AI*IA '99 Proceedings of the 6th Congress of the Italian Association for Artificial Intelligence on Advances in Artificial Intelligence
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Information and Computation - Special issue: LICS'97
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
Applying GSAT to non-clausal formulas
Journal of Artificial Intelligence Research
Equivalence checking of combinational circuits using Boolean expression diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present an algorithm for determining satisfiability of general Boolean formulas which are not necessarily on conjunctive normal form. The algorithm extends the well-known Davis-Putnam algorithm to work on Boolean formulas represented using Boolean Expression Diagrams (BEDs). The BED data structure allows the algorithm to take advantage of the built-in reduction rules and the sharing of sub-formulas. Furthermore, it is possible to combine the algorithm with traditional BDD construction (using Bryant's APPLY-procedure). By adjusting a single parameter to the BedSat algorithm it is possible to control to what extent the algorithm behaves like the APPLY-algorithm or like a SAT-solver. Thus the algorithm can be seen as bridging the gap between standard SAT-solvers and BDDs. We present promising experimental results for 566 non-clausal formulas obtained from the multi-level combinational circuits in the ISCAS'85 benchmark suite and from performing model checking of a shift-and-add multiplier.