Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Emulation of biological networks in reconfigurable hardware
Proceedings of the 2nd ACM Conference on Bioinformatics, Computational Biology and Biomedicine
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Recent work has presented logical models and showed the benefits of applying logical approaches to studying the dynamics of biological networks. In this work, we develop a methodology for automating the design of such models by utilizing methods and algorithms from the field of electronic design automation. We anticipate that automated discrete model development will greatly improve the efficiency of qualitative analysis of biological networks.