Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
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A communication protocol usually represents a system whose behavior can be specified through a finite state machine. Finite state machines are often used to model digital systems in the context of logic synthesis and formal hardware verification. Therefore, sophisticated and efficient tools (for example, hardware simulators) to analyze this type of systems do exist.In this paper, we propose an approach to the verification and performance evaluation of communication protocols and, in general, of entire computer networks based on VHDL modeling and simulation. The results we have obtained on a few case studies (some of which are reported in this paper) seem to indicate the feasibility of the method.