Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Amap: A technology mapper for selector-based field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
USING IF-THEN-ELSE DAGS TO DO TECHNOLOGY MAPPING FOR FIELD-PROGRAMMABLE GATE ARRAYS
USING IF-THEN-ELSE DAGS TO DO TECHNOLOGY MAPPING FOR FIELD-PROGRAMMABLE GATE ARRAYS
On designing ULM-based FPGA logic modules
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Series-parallel functions and FPGA logic module design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using BDDs to design ULMs for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Universal logic modules for series-parallel functions
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Using Decision Diagrams to Design ULMs for FPGAs
IEEE Transactions on Computers
Generation of universal series-parallel Boolean functions
Journal of the ACM (JACM)
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper the problem of selecting an appropriate programmable cell structure for FPGA architecture design is addressed. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. A general methodology to determine logic description of such cells, which are capable of being configured to a given set of functions is described.Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power but requires substantially less area and wiring overhead.