Universal logic gate for FPGA design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On designing ULM-based FPGA logic modules
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Series-parallel functions and FPGA logic module design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using BDDs to design ULMs for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Universal logic modules for series-parallel functions
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
On the Construction of Universal Series-Parallel Functions for Logic Module Design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique in FTGA design, it is desirable to design FPGA logic modules based on Boolan functions which can be represented by a tree of gates (i.e., series-parallel or SP functions). Thakur and Wong [1996a; 1996b] studied this issue and they demonstrated the advantages of designing logic modules as universal SP functions, that is, SP functions which can implement all SP functions with a certain number of inputs. The number of variables in the universal function corresponds to the number of inputs to the FPGA module, so it is desirable to have as few variables as possible in the constructed functions. The universal SP functions presented in Thakur and Wong [1996a; 1966b] were designed manually. Recently, there is an algorithm that can generate these functions automatically [Young and Wong 1997], but the number of variables in the generated functions grows exponentially. In this paper, we present an algorithm to generate, for each n 0, a universal SP function fn for implementing all SP functions with n inputs or less. The number of variables in fn is less than n2.376 and the constructions are the smallest possible when n is small (n ≤ 7). We also derived a nontrival lower bound on the sizes of the optimal universal SP functions (&OHgr;(n log n)).