Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Finding reset nondeterminism in RTL designs: scalable X-analysis methodology and case study
Proceedings of the Conference on Design, Automation and Test in Europe
A compact encoding of pseudo-boolean constraints into SAT
KI'12 Proceedings of the 35th Annual German conference on Advances in Artificial Intelligence
Verifying refutations with extended resolution
CADE'13 Proceedings of the 24th international conference on Automated Deduction
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Automatic synchronization (or reset) of sequential synchronous circuits is considered one of the most challenging tasks in the domain of formal sequential equivalence verification of hardware designs. Earlier attempts were based on Binary Decision Diagrams (BDDs) or classical reachability analysis, which by nature suffer from capacity limitations. A previous attempt to attack this problem using non-BDD based techniques was essentially a collection of heuristics aimed at toggling of the latches, and it is not guaranteed that a synchronization sequence will be computed if it exists. In this paper we present a novel approach for computing reset sequences (and reset states) in order to perform sequential hardware equivalence verification between circuit models. This approach is based on the dual-rail modeling of circuits and utilizes efficient SAT-based engines for Bounded Model Checking (BMC). It is implemented in Intel's sequential verification tool, Seqver, and has been proven to be highly successful in proving the equivalence of complex industrial designs. The synchronization method described in this paper can be used in many other CAD applications, including formal property verification, automatic test generation, and power estimation.