Performance optimization of sequential circuits by eliminating retiming bottlenecks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integration, the VLSI Journal
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The timing optimization of multiphase logic entails the reduction of the overall cycle time of the machine and/or input-to-output delays by distributing computation throughout the entire clock cycle. A tool has been developed to automatically perform this optimization task, and it has been implemented as a set of extensions to the combinational logic optimization tool, misII. The algorithms yield improvements that are on average 10-20% better than what is achievable using purely combinational logic optimization tools that do not move logic across latches. These improvements represent 75% of what would be possible in the most idealized case. Results on simple two-phase circuits show average input-to-output delay improvements of 13% with area penalties of 11%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 18% with an area penalty of 11%. Experiments indicate that the optimization algorithm is highly insensitive to parameter variations in the underlying combinational logic optimization routines and initial state assignment