Circuit structure relations to redundancy and delay: the KMS algorithm revisited
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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All existing algorithms for clock schedule optimization are conservative since they use only topological analysis to estimate the delays of paths between latches. This paper proposes a novel algorithm that accounts for false paths (over several time frames) in level-sensitive sequential circuits to obtain tighter bounds on the optimum clock schedule than previously obtainable.