ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SIAM Journal on Scientific Computing
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Computer-aided control system design using optimization methods
Computer-aided control system design using optimization methods
Analysis and design of latch-controlled synchronous digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we have modelled the flip-flop clock to output delay dependency on the data arrival time and introduced this phenomenon in timing analysis. Traditionally, finding the minimum clock period of a flip-flop based sequential design was based on the assumption that the setup-time and clock to output delay of a flip-flop are constant and hence each stage of the pipeline can be analyzed independently. However, it is well known that the delay of a flip-flop depends on the data arrival time at its input and hence there exists an interdependence among different pipeline stages. The problem of finding the minimum clock period of such a coupled system is a non-trivial problem. In this paper, we formu-late the problem of finding the minimum clock period of a flip-flop based sequential circuit accounting for these dependencies. We show that the problem is a non-linear convex optimization problem. We propose three different solution approaches and compare their results on ISCAS '89 sequential benchmark circuits. Modeling these data arrival time dependencies we have seen a consistent decrement of approximately 50-60ps compared to the traditional approach using constant setup-time and flip-flop delays. We also show how the analysis can be extended to account for hold time constraints for short paths in the circuit.