Bounding Switching Activity in CMOS Circuits Using Constraint Resolution

Authors:
J. Zejda;E. Cerny;S. Shenoy;N. C. Rumin
Affiliations:
Dép. I.R.O., Université de Montréal, C.P. 6128, Succ. Centre Ville, Montréal (Québec), H3C 3J7, Canada;Dép. I.R.O., Université de Montréal, C.P. 6128, Succ. Centre Ville, Montréal (Québec), H3C 3J7, Canada;Dept. of EE, McGill University, 3480 University Street, Montreal (Quebec), H3A 2A7, Canada;Dept. of EE, McGill University, 3480 University Street, Montreal (Quebec), H3A 2A7, Canada
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 4
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Abstract

This paper deals with the problem of estimating the average power consumption (per clock cycle) of CMOS digital circuits. A new pattern-independent method is proposed for computing an upper bound on the switching activity, and therefore the average power, of a combinational circuit described at the gate level. The method is based on the propagation of abstract waveform sets, described down to the level of individual transitions. The view of a gate as a relation between input and output signals, described by forward and partial inverse functions, permits the determination of a tight upper bound on the power using a constraint resolution method based on waveform narrowing. A fully scalable, case analysis-based algorithm provides at any step an upper bound and, with enough resources (CPU time), it can continue up to the exact solution. The paper presents the theoretical background, a description of the implementation, and results on benchmark circuits.