Accelerated Compact Test Set Generation for Three-State Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Invalid State Identification for Sequential Circuit Test Generation
ATS '96 Proceedings of the 5th Asian Test Symposium
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Compact test sets for industrial circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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TPG for synchronous sequential circuits has receivedwide attention over the last two decades, yet unlike for(full-scan) combinational circuits, for many sequentialbenchmark circuits 100% fault efficiency still cannot bereached. This illustrates the complexity of sequentialcircuit ATPG.The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity.Powerful techniques and heuristics are required to copewith this search space. One way to reduce the searchspace is the detection of illegal states. These states cannot be justified with an initialization sequence.In this paper, we propose new techniques to find illegal states and to remove the over-specification of thesestates by searching common fractions in the list of illegal states. Experimental results demonstrate the importance of an as complete as possible illegal state list:Higher fault efficiencies are reached for the sequentialISCAS '89 circuits [1] and industrial circuits, togetherwith a large reduction of CPU time.