Error-control coding for computer systems
Error-control coding for computer systems
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder
ISPAN '99 Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks
New degree computationless modified euclid algorithm and architecture for reed-solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Integrated ECC-MAC Based on RS Code
Transactions on Computational Science IV
New architectural design of CA-based codec
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Null boundary 90/150 cellular automata for multi-byte error correcting code
ACRI'10 Proceedings of the 9th international conference on Cellular automata for research and industry
| Hi-index | 0.00 |
Cellular Automata(CA) based VLSI implementation of t-byte errors correcting code has been established by previous research to be superior to the other existing techniques employed for realizing Reed-Solomon(RS) code. However, the scheme suffers from the limitation that it can correct t茂戮驴byte errors (t茂戮驴 2) provided errors are confined either wholly to the information bytes or entirely to the check bytes. The work reported in the present paper overcomes this limitation and corrects the errors likely in both information and check bytes. Moreover one weakness found in an earlier similar work has been identified and rectified using a modified check symbol expressions.