Error-correcting codes for byte-organized memory systems
IEEE Transactions on Information Theory
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder
ISPAN '99 Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks
Design and Implementation of RS (32, 28) Encoder and Decoder Using Cellular Automata
ADCOM '07 Proceedings of the 15th International Conference on Advanced Computing and Communications
An Improved Double Byte Error Correcting Code Using Cellular Automata
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
Null boundary 90/150 cellular automata for multi-byte error correcting code
ACRI'10 Proceedings of the 9th international conference on Cellular automata for research and industry
| Hi-index | 0.00 |
Cellular automata (CA) has already established its novelty for bits and bytes error correcting codes (ECC). The current work identifies weakness and limitation of existing CA-based byte ECC and proposes an improved CA-based double byte ECC which overcomes the identified weakness. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed-Solomon (RS) Codes. Also it has been shown that the CA-based scheme can easily be extended for correcting more than two byte errors.