Error-correcting codes for byte-organized memory systems
IEEE Transactions on Information Theory
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
Application of GF(2p) CA in Burst Error Correcting Codes
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder
ISPAN '99 Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks
An Improved Double Byte Error Correcting Code Using Cellular Automata
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
An Integrated ECC-MAC Based on RS Code
Transactions on Computational Science IV
New architectural design of CA-based codec
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Cellular Automata(CA) is a well known tool to generate byte error correcting code. In this paper, we propose a CA-based multibyte Error Correcting Code (ECC) which overcomes the weaknesses and limitation of existing scheme. As a case study three and four bytes ECC are discussed in detailed. A complete decoding algorithm of CAbased 3-byte error correcting code is presented in this work. Proposed 3-byte ECC scheme can correct errors when errors are distributed within information and check bytes or concentrated in any one of them. In case of CA-based 4-byte ECC, at most 4-byte errors can be corrected if all the errors are concentrated in information or check bytes.