Error-control coding for computer systems
Error-control coding for computer systems
Coding and information theory
Designs and their codes
Proceedings of the 15th symposium on Integrated circuits and systems design
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
Journal of Electronic Testing: Theory and Applications
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
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Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected to be less reliable, to have high defect density and to be handled with effective defect tolerant techniques. Thus, reliability is a major challenge in the future of IC design. To this end, different coding techniques have been proposed to improve reliability of future technologies. In this paper we analyze the trade-off between the area and the reliability added in each chip employing the Reed Muller coding as the coding technique. We estimate the reliability and area increase of different orders of the Reed Muller decoding and observed that while the area increases, the reliability decreases. Our approach is to define a framework and help designers in order to decide on the configuration of the Reed Muller to be used. Finally, we provide a guideline to optimize the architecture making an optimal trade off between the area and the reliability.