Error-control coding for computer systems
Error-control coding for computer systems
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Optimal Two-Level Unequal Error Control Codes for Computer Systems
IEEE Transactions on Computers
Optimal two-level unequal error control codes for computer systems
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Two error-detecting and correcting circuits for space applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
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Abstract: Error control codes are now being successfully applied to computer systems, especially to memory systems. This paper proposes a new class of error control codes to protect the fixed-byte in computer words from errors. The fixed-byte stores valuable and important information such as control and address information in communication messages or pointer information in database words. 'Fixed-byte' means the clustered information digits in the word whose position is determined in advance. As a simple class of these unequal error protection codes, this paper proposes two types of optimal fixed-byte error protection codes: single-bit error correction and fixed b-bit byte error correction (SEC-FbEC) codes and single-bit error correction, double-bit error detection, and fixed b-bit byte error detection (SEC-DED-FbED) codes. The obtained optimal SEC-FbEC codes where byte length b=7 bits and information length k=64 bits, for example, require a check-bit length of only 8 bits, which is the same as that of the conventional SEC-DED codes with k=64 bits.