Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Note on Self-Checking Checkers
IEEE Transactions on Computers
A Design Technique of TSC Checker for Borden's Code
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Design of t-UED/AUED Codes from Berger's AUED Code
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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A testable design of a programmable m-out-of-n code checker is reported in this paper. The checker is modular in nature and can be easily extended by cascading. Basically, a cellular automaton (CA) structure is taken whose combinational logic port (CL-part) is modified in such a way that all the 1's in the initial state (seed) get accumulated in the rightmost cells. This CA is then transformed into an iterative array of combinational logic cells. To make the resulting structure testable for all stuck-at and unidirectional faults, it is partitioned into a number of identical blocks the outputs of which are combined to produce two complementary outputs.