A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-

Authors:
Mitsuru Hamada;Eiji Fujiwara
Affiliations:
Univ. of Electro-Communications, Tokyo, Japan;Tokyo Institute of Technology, Tokyo, Japan
Venue:
IEEE Transactions on Computers
Year:
1997

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Abstract

A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b驴 2, and more efficient than previously known codes with as strong error control capabilities.