Comments on "Carry checking/parity prediction adders and ALUs"

Authors:
José J. Rodríguez-Navarro
Affiliations:
MED-EL Medical Electronics, Innsbruck, Austria and RWTH Aachen University, Aachen, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Error-control coding for computer systems

Error-control coding for computer systems
Carry checking/parity prediction adders and ALUs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

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Abstract

In this brief, it is shown that the checking or comparison of normal carries versus duplicated carries in a carry checking/parity prediction adder can be partially avoided, making it feasible to implement a less complex checker when using a robust logic style.