Lookaside Techniques for Minimum Circuit Memory Translators
IEEE Transactions on Computers
Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement
IEEE Transactions on Computers
Implementation of an Experimental Fault-Tolerant Memory System
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM Journal of Research and Development
Convolutionally Encoded Memory Protection
IEEE Transactions on Computers
IEEE Transactions on Information Forensics and Security
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 14.98 |
In this paper we introduce and evaluate error correction methods which takes into account the special properties of failure modes in semiconductor memories. We assume that the memory faults are of the type stuck-to 1 or 0. Thus the fault, once it has occurred, is located to a specific position in a memory word. The position may be found and this fact makes it convenient to use erasure correction, rather than random error correction.