A Robust Matrix-Multiplication Array

Authors:
P. J. Varman;I. V. Ramakrishnan;D. S. Fussell
Affiliations:
Department of Electrical and Computer Engineering, Rice University;-;-
Venue:
IEEE Transactions on Computers
Year:
1984

Citing 5
Cited 0

Introduction to VLSI Systems

Introduction to VLSI Systems
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays

IEEE Transactions on Computers
Design of a Massively Parallel Processor

IEEE Transactions on Computers
Why Systolic Architectures?

Computer
Introduction to the Configurable, Highly Parallel Computer

Computer

Quantified Score

Hi-index	14.98

Visualization

Abstract

Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size. Multiplication of two n x n matrices requires O(n) processors and has a time complexity of O(n2) cydes.