A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
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A number of parallel, MIMD architectures for continuous system simulation have been proposed, some designed and a few implemented [Korn,72], [Cyre et.al.,77], [Halin,et.al. 80] over the past few years. While these architectures vary in several aspects such as interconnection structures, processor components used etc., there is a strong similarity between them that arises from the problem at hand. This is the need for a controller or master processor that can control the flow of data between a group of subprocessors, and also initiate execution when required data are available. It is possible however to take a substantially different approach to the problem. In the data-flow approach [Rumbaugh,77], [Dennis,75] the data dependency of each instruction is explicit. An instruction gets executed only when the data for it are available. A general unrestricted data flow machine, while quite attractive, is a substantially difficult venture. But, with a few restrictions on the capability, a much less expensive machine is possible, that is still quite powerful for purposes such as continuous simulation. The present paper focuses on a survey and analysis of methods appropriate for continuous system simulation on such an architecture. However some key characteristics of this architecture must be appreciated before the analysis can be done.