Run-time generation of HPS microinstructions from a VAX instruction stream
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Checkpoint repair for out-of-order execution machines
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
High-bandwidth/low-latency temporary storage for supercomputers
High-bandwidth/low-latency temporary storage for supercomputers
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The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the micro VAX subset, and report the results of varying (i.e. tuning) certain important parameters.