A list-processing-oriented data flow machine architecture

Authors:
Makoto Amamiya;Ryuzo Hasegawa;Osamu Nakamura;Hirohide Mikami
Affiliations:
Musashino Electrical Communication Laboratory, N.T.T., Tokyo, Japan;Musashino Electrical Communication Laboratory, N.T.T., Tokyo, Japan;Musashino Electrical Communication Laboratory, N.T.T., Tokyo, Japan;Musashino Electrical Communication Laboratory, N.T.T., Tokyo, Japan
Venue:
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Year:
1982

Citing 3
Cited 1

Guarded commands, nondeterminacy and formal derivation of programs

Communications of the ACM
A preliminary architecture for a basic data-flow processor

ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
The architecture and system method of DDM1: A recursively structured Data Driven Machine

ISCA '78 Proceedings of the 5th annual symposium on Computer architecture

DFSP: A Data Flow Signal Processor

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper analyzes some issues concerning list processing under a data flow control environment from the viewpoint of parallelism and also presents a new type of list-processing-oriented data flow machine, based on an association memory and logic-in-memory. The mechanism of partial execution in each function is shown by example to be effective in exploiting the parallelism in list processing. The lenient cons mechanism is shown to exploit maximally parallelism among activated functions.