A computer simulation facility for packet communication architecture

Authors:
Clement K.C. Leung;David P. Misunas;Andrij Neczwid;Jack B. Dennis
Affiliations:
Project MAC, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139;Project MAC, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139;Project MAC, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139;Project MAC, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139
Venue:
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Year:
1976

Citing 2
Cited 0

A preliminary architecture for a basic data-flow processor

ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Programming with abstract data types

Proceedings of the ACM SIGPLAN symposium on Very high level languages

Quantified Score

Hi-index	0.00

Visualization

Abstract

Several proposals for computer data processing and memory systems that exploit the inherent parallelism in programs expressed in data flow form have been advanced recently. These systems have packet communication architecture—each system consists of many units that interact only through the transmission of information packets through channels that link pairs of units. A simulation facility for evaluating the programmability and potential performance of these proposed data processing and memory systems has been designed. The facility uses microprocessor modules to emulate the behavior of system units or groups of units. By conducting a simulation in accurate scale time a precise extrapolation of performance of a proposed system may be obtained. The user of the facility will specify the system to be simulated in an architecture description language. A host computer translates the system description modules into microprocessor programs and controls the loading and monitors the operation of the microprocessors. Application of the facility is illustrated by consideration of a simple data flow processor.