On tuning the microarchitecture of an HPS implementation of the VAX

Authors:
James E. Wilson;Steve Melvin;Michael Shebanow;Wen-mei Hwu;Yale N. Patt
Affiliations:
Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA
Venue:
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Year:
1987

Citing 5
Cited 1

HPS, a new microarchitecture: rationale and introduction

MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Run-time generation of HPS microinstructions from a VAX instruction stream

MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Checkpoint repair for out-of-order execution machines

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A preliminary architecture for a basic data-flow processor

ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
High-bandwidth/low-latency temporary storage for supercomputers

High-bandwidth/low-latency temporary storage for supercomputers

Improving CISC instruction decoding performance using a fill unit

Proceedings of the 28th annual international symposium on Microarchitecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the microVAX subset, and report the results of varying (i.e. tuning) certain important parameters.