Communications of the ACM
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Reduction languages for reduction machines
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
A concurrent computer architecture and a ring based implementation
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
The architecture and system method of DDM1: A recursively structured Data Driven Machine
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Interpreting machines: Architecture and programming of the B1700/B1800 series (Operating and programming systems series)
Survey on special purpose computer architectures for AI
ACM SIGART Bulletin
Grammars for functional languages
CSC '86 Proceedings of the 1986 ACM fourteenth annual conference on Computer science
Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
A system architecture for the concurrent evaluation of applicative program expressions
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A recursive computer architecture for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A preliminary survey of artificial intelligence machines
ACM SIGART Bulletin
Cooperating Reduction Machines
IEEE Transactions on Computers
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The design of a multi-processor reduction machine, supporting a class of user-defined reduction languages, is presented. A reduction machine is based on a “by need” or demand driven model of computation in which an instruction is executed only when a result it generates is requested. In such a machine, an instruction is a (variable length and possibly nested) expression and the machine language is referred to as a reduction language. In the multi-processor reduction machine presented, the asynchronous operation of a processor is controlled by a swappable, user-defined, state transition table. Each table supports a particular reduction language. To ensure the harmonious operation of the processors a state transition table is generated automatically for a user, in a similar way that a parser generator is used to generate table driven parsers.