The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
Multiprocessor Organization—a Survey
ACM Computing Surveys (CSUR)
Communications of the ACM
Protection in an information processing utility
Communications of the ACM
Operating system principles
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
The minerva multi-microprocessor
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Multiprocessor Architectures For Concurrent Programs
ACM '78 Proceedings of the 1978 annual conference
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
The Architecture of SM3: A Dynamically Partitionable Multicomputer System
IEEE Transactions on Computers
The ETH-Multiprocessor Empress: A Dynamically Configurable MIMD System
IEEE Transactions on Computers
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A computer architecture for concurrent computing is proposed that has the shared memory aspect of tightly coupled multiprocessor systems and also the connection simplicity associated with message-connected, loosely coupled multicomputer systems. A large address space is dynamically partitioned into contiguous segments that can be accessed by a single processor. The partitioning is accomplished by switching the system buses, using semiconductor switches. The completion of a concurrent process is signaled by a processor's return to an idle state and the reattachment of its memory segment to the neighboring active processor. In effect, the assignment of an address sequence and the activation of a processor is a process FORK operation, and the processor deactivation and memory segment reattachment is a process JOIN. Following a description of the MP/C structure and basic operation, some additional enhancements of the system, which improve the applicability of MP/C to many classes of computations, are outlined. Applications include tree-structured multiprocessing, recursive and nondeterministic procedures, arbitrary concurrent computations, very high precision numeric calculations, and process-structured operating systems. The linear MP/C structure is extensible to higher dimensions. A two-dimensional system is described, and its usefulness for data base operations and array processing is discussed.