Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
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The aim of the paper is to present the carrying out of an on-chip system (SOC) round about of an on-chip network (NOC) implemented on a FPGA structure. The hardware system is developed in order to control an autonomous mobile device that is able to search and track a mobile target detecting and avoiding all the obstacles in its route. The control device consists mainly of two components: 1) Sensorial (Intelligent Sensors) for searching the target and for detection of the obstacles and 2) Informatic System that analyzes and control the information taken over from the sensors, recognizes the target, establishes the route to go on. The sensorial component is made up of a great number of various sensors, especially selected and mounted, in order to obtain as much information as possible from these about the environment where the robot is moving. The informatics component is carried out entirely on a reprogrammable device FPGA. The on-chip system (SoC) that is developed is practically a network of functional units that have to receive raw data from the sensors and to transform it in as much useful information as possible. For each sensor is designed an (intelligent) unit of this description. Because of the great number of sensors, these units are interconnected through an internal network (network on-chip NOC).