A practical design and implementation of on-chip NI for integrating bus based IP legacies

Authors:
Jung-Ho Lee;Sin-Chong Park
Affiliations:
Information and Communications University, System Integration Technology Institute, Munjiro, Yuseong-gu, Daejeon, Korea;Information and Communications University, System Integration Technology Institute, Munjiro, Yuseong-gu, Daejeon, Korea
Venue:
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Year:
2007

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Abstract

Decoupling communication and computation by adapting on-chip network has already become an irreversible trend, as we proceed into deeper sub-micron era. Nevertheless, innumerable number of IP cores is developed for conventional bus protocol. Brute force aggregation of bus based IP cores is not a good idea, because it can cause excessive load on on-chip network, by stalling routers and network interfaces. Therefore, for a bus based IP usually has better performance when it is plugged into a local bus with dedicated components which have high affinity with the core. This paper argues practical design and implementation issues of NI for on-chip network interconnection between bus-connected components. Implemented system gives out waveform with significantly small latency of packetization at the clock boundary.