Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
| Hi-index | 0.00 |
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6% increase in throughput and 76.53% decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9% reduction in resources, 548% increase in throughput and 84.7% reduction in latency.