High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Two-dimensional round-robin schedulers for packet switches with multiple input queues
IEEE/ACM Transactions on Networking (TON)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
Tiny Tera: A Packet Switch Core
IEEE Micro
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Control architecture in optical burst-switched WDM networks
IEEE Journal on Selected Areas in Communications
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A packet-aware non-interleaving scheduling algorithm that has multiple classes according to the packet lengths is proposed, and the latencies and buffer requirement are investigated in comparison with other algorithms. The non-interleaving scheduling algorithm eliminates the complexity of packet reassembly at the output queue. The simulated results show that the packet-aware non-interleaving scheduling inherently improves the latency of the long packets, while the proposed multi-class scheduling complementarily improves the latency of the short packets. The results show that the non-interleaving algorithm is not only feasible for the practical implementation but may have better performance in the latency, output buffer requirement, and implementation complexity viewpoints, if appropriate scheduling algorithm is used. The simulated results are obtained using self-similar traffic generated based on the measured Internet backbone traffic that reflects the predominance of short packets.