Request Resubmission in a Blocking, Circuit-Switched, Interconnection Network
IEEE Transactions on Computers
Tiny Tera: A Packet Switch Core
IEEE Micro
Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor Communications
IEEE Transactions on Parallel and Distributed Systems
Design of a Gigabit ATM Switch
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
Scheduling multicast cells in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Architecture, performance, and implementation of the tandem banyan fast packet switch
IEEE Journal on Selected Areas in Communications
Architecture of a packet switch based on banyan switching network with feedback loops
IEEE Journal on Selected Areas in Communications
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
| Hi-index | 0.24 |
This paper describes the design of a centralized controller/scheduler for a communication switch with a banyan switching fabric built using unbuffered switches. The controller accepts a set of connection requirements and identifies a non-conflicting subset that can be used to set the state of the switches for data transfer. The logic can be implemented using a relatively small number of gates and can be pipelined to provide rapid control of the switch fabric. The controller can be used with any replicated banyan network fabric that provides sufficient switching speed and data bandwidth.