Optimal buffer management policies for shared-buffer ATM switches
IEEE/ACM Transactions on Networking (TON)
Analytical models for replicate-at-send multicasting in shared-memory switches
Performance Evaluation
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
MCA: a single chip one-port scalable ATM layer controller
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Journal of Electrical and Computer Engineering
Review: Review of recent shared memory based ATM switches
Computer Communications
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The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 μm CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32×8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 μm pure CMOS technology. By using four chip sets, a 622 Mbit/s 32×32 switch can be installed on one board