Wormhole IP over (connectionless) ATM

  • Authors:

  • Manolis G. H. Katevenis;Iakovos Mavroidis;Georgios Sapountzis;Eva Kalyvianaki;Ioannis Mavroidis;Georgios Glykopoulos

  • Affiliations:

  • ICS-FORTH, Heraklion, Crete, GR-711.10 Greece, and University of Crete, Heraklion, Crete, Greece;MIPS Technologies, Mountain View, CA;ICS-FORTH, Heraklion, Crete, GR-711.10 Greece, and University of Crete, Heraklion, Crete, Greece;ICS-FORTH, Heraklion, Crete, GR-711.10 Greece, and University of Crete, Heraklion, Crete, Greece;Applied Micro Circuits Corporation, Andover, MA;Globetechsolutions Inc., Thessaloniki, Greece

  • Venue:
  • IEEE/ACM Transactions on Networking (TON)
  • Year:
  • 2001

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Abstract

High-speed switches and routers internally operate using fixed-size cells or segments; variable-size packets are segmented and later reassembled. Connectionless ATM was proposed to quickly carry IP packets segmented into cells (AAL5) using a number of hardware-managed ATM VCs. We show that this is analogous to wormhole routing. We modify this architecture to make it applicable to existing ATM equipment: we propose a low-cost, single-input, single-output Wormhole IP Router that functions as a VP/VC translation filter between ATM subnetworks. When compared to IP routers, the proposed architecture features simpler hardware and lower latency. When compared to software-based IP-over-ATM techniques, the new architecture avoids the overheads of a large number of labels, or the delays of establishing new flows in software after the first few packets have suffered considerable latencies. We simulated a wormhole IP routing filter, showing that a few tens of hardware-managed VCs per outgoing VP usually suffice. We built and successfully tested a prototype, operating at 2 × 155 Mb/s, using one field programmable gate array (FPGA) and DRAM. Simple analysis shows that operation at 10 Gb/s and beyond is feasible today.