The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Optical solutions for system-level interconnect
Proceedings of the 2004 international workshop on System level interconnect prediction
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
CMOS Photonics for High-Speed Interconnects
IEEE Micro
Exploitation of optical interconnects in future server architectures
IBM Journal of Research and Development - POWER5 and packaging
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
BLOCON: a bufferless photonic Clos Network-on-Chip architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Two-hop free-space based optical interconnects for chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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Network-on-Chips (NoCs) are becoming the defacto standard for interconnecting the increasing number of cores in chip multiprocessors (CMPs) by overcoming the scalability and wire delay problems of shared buses. However, recent research has shown that future NoCs will be limited by power dissipation and reduced performance forcing architects to explore other technologies that are complementary metal oxide semiconductor (CMOS) compatible. In this paper, we propose ET-PROPEL (Extended Token based Photonic Reconfigurable On-Chip Power and Area-Efficient Links) architecture to utilize the emerging nanophotonic technology to design a high-bandwidth, low latency and low power multi-level hybrid interconnect that balances cost and performance. We develop our interconnect at three levels: at the first level (x) we design a fully connected network for exploiting locality; at the second level(y), we design a shared channel using optical tokens to reduce power while providing full connectivity and at the third level (z), we propose a novel nanophotonic crossbar that provides scalable bisection bandwidth. The first two levels are combined into T-PROPEL(token-PROPEL, 64 cores) and four separate T-PROPELs are combined into ET-PROPEL (256 cores). We have simulated both T-PROPEL and ET-PROPEL using synthetic and SPLASH-2 traffic, where our results indicate that T-PROPEL and ET-PROPEL significantly reduce power(10-fold) and increase performance (3-fold) over other well known electrical and photonic networks.