HANDS: heterogeneous architectures and networks-on-chip design and simulation

Authors:
Davide Zoni;Simone Corbetta;William Fornaciari
Affiliations:
Politecnico di Milano, Milano, Italy;Politecnico di Milano, Milano, Italy;Politecnico di Milano, Milano, Italy
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

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Abstract

In current multi-core scenario, Networks-on-Chip (NoC) represent a suitable choice to face the increasing communication and performance requirements, however introducing additional design challenges to already complex architectures. In this perspective, there is a need for flexible and configurable virtual platforms for early-stage design exploration. We present the Heterogeneous Architectures and Networks-on-Chip Design and Simulation framework for large-scale high-performance computer simulation, integrating performance, power, thermal and reliability metrics under a unique methodology. Moreover, NoC exploration is possible from a reliability/performance and thermal/performance trade-offs.