System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Heterogeneous Modelling of an Optical Network-on-Chip with SystemC
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Chip multiprocessing and the cell broadband engine
Proceedings of the 3rd conference on Computing frontiers
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
A Nanophotonic Interconnect for High-Performance Many-Core Computation
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Optical Network on Chip (ONoC) architectures are emerging as promising candidates to solve congestion and latency issues in future embedded systems. In this work, we examine how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in heterogeneous 3D architectures. Through such techniques, it is possible to reduce the number of required wavelengths, laser sources, photodetectors and optical switches as well as the length of the longest optical path. This allows constraints to be relaxed on source wavelength accuracy and passive filter selectivity, and also alleviates power and area issues by reducing the number of active devices. The proposed reduction method was successfully applied to multiple heterogeneous 3D architectures.