LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures

Authors:
Cheng Li;Mark Browning;Paul V. Gratz;Samuel Palermo
Affiliations:
Texas A&M University, College Station, TX, USA;Texas A&M University, College Station, TX, USA;Texas A&M University, College Station, TX, USA;Texas A&M University, College Station, TX, USA
Venue:
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Year:
2012

Citing 2
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Abstract

Achieving scaling performance as core counts increase to the hundreds in future chip-multi-processors (CMPs) requires high performing, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50% lower latency at low loads and 40% higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies 40% versus an electrical 2D mesh NoCs on the PARSEC shared memory, multithreaded benchmark suite.