Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Optimal phase conflict removal for layout of dark field alternating phase shifting masks
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
Practical iterated fill synthesis for CMP uniformity
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2001 international symposium on Physical design
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
New and Exact Filling Algorithms for Layout Density Control
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Reticle enhancement technology: implications and challenges for physical design
Proceedings of the 38th annual Design Automation Conference
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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In this paper, we briefly describe the lithography developments known as RET (Resolution Enhancement Technologies),which include off-axis illumination in litho tools,Optical and Process Correction (OPC), and phase shifting masks (PSM). All of these techniques are adopted to allow ever smaller features to be reliably manufactured, and are being generally adopted in all manufacturing below 0.25 microns. However, their adoption also places certain restrictions on layouts. We explore these restrictions, and then provide suggestions for layout practices that will facilitate the use of these technologies, especially the generation of a clean target layout for use as input layers for photomask preparation, and the use of verification tools that use process simulation.