Importance sampled circuit learning ensembles for robust analog IC design

Authors:
Peng Gao;Trent McConaghy;Georges Gielen
Affiliations:
ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium;ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium and Solido Design Automation Inc., Saskatoon, Canada;ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium
Venue:
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Year:
2008

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Abstract

This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore's Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an ISCLEs-specific library of possible digital-sized circuit blocks; and (3) a recently-developed multi-topology sizing technique to automatically determine each block's topology and device sizes. ISCLEs is demonstrated on design of a sinusoidal function generator and a flash A/D converter, showing promise to robustly scale with shrinking process geometries.