ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Low leakage power datapaths can be synthesized usingMulti-Threshold CMOS (MTCMOS) modules. MTCMOS modules can be turnedON or OFF, using sleep signals. The controller in a digital systemcan be automatically synthesized to generate these sleep signals toturn OFF idle modules, thus minimizing leakage power. In order tosustain performance, the sleep transistor needs to be sized tolarge widths. This leads to a significant area overhead. In thiswork, we propose a binding algorithm, based on the 0-1 Knapsackalgorithm, to selectively bind modules in a datapath to MTCMOSmodules, achieving the optimizing leakage power within a given areaconstraint. We present results for five data dominated DSPcircuits, at 100nm technology node.