Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of Low-Impedance Substrate on Power Supply Integrity
IEEE Design & Test
Chip Substrate Resistance Modeling Technique for Integrated Circuit Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This brief discusses the impact of twin- and triple-well structures on power supply noise, and a substrate model for simulating the power supply noise. We observed Vss noise reduction by the resistive network of the p-substrate and Vdd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triple-well structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.