A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Authors:
Yu-Min Lee;Charlie Chung-Ping Chen
Affiliations:
University of Wisconsin at Madison, Madison, WI;University of Wisconsin at Madison, Madison, WI
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block based followed by global analysis on the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5% of accuracy.