Discrete-time signal processing
Discrete-time signal processing
A straightforward ΣΔ fractional-N phase-locked loop HDL design for RF applications
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents the behavioral model of a Ε-Δ fractional-N frequency synthesizer in terms of different noise sources and non-ideal effects. To accurately predict the phase noise of the synthesizer, different jitter noise sources such as phase modulation (PM) noise in phase-frequency detector and divider, frequency modulation (FM) noise in VCO are properly depicted. The Ε-Δ modulator, with its divider value dithered and quantization noise dynamically injected to the PLL, is described in behavioral model, which allows the designer to study the quantization noise impaction to the PLL phase noise. All the models are implemented in VHDL-AMS and simulated using Mentor Graphics ADvance-MS (ADMS). Our behavioral modeling method enables a fast simulation of the PLL system and an accurate phase noise prediction.