An Efficient Approach to Build Accurate Behavioral Models of PLL Designs

Authors:
Chin-Cheng Kuo;Yu-Chien Wang;Chien-Nan Jimmy Liu
Affiliations:
The authors are with the Department of Electrical Engineering, National Central University, Taiwan, R.O.C. E-mail: 92521014@cc.ncu.edu.tw;The authors are with the Department of Electrical Engineering, National Central University, Taiwan, R.O.C. E-mail: 92521014@cc.ncu.edu.tw;The authors are with the Department of Electrical Engineering, National Central University, Taiwan, R.O.C. E-mail: 92521014@cc.ncu.edu.tw
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2006

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Abstract

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.