Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration

Authors:
Geng Zheng;Saraju P. Mohanty;Elias Kougianos;Oleg Garitselov
Affiliations:
University of North Texas, Denton, TX, USA;University of North Texas, Denton, TX, USA;University of North Texas, Denton, TX, USA;University of North Texas, Denton, TX, USA
Venue:
Proceedings of the great lakes symposium on VLSI
Year:
2012

Citing 5
Cited 0

An Efficient Approach to Build Accurate Behavioral Models of PLL Designs

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space

VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters

VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study

ISED '10 Proceedings of the 2010 International Symposium on Electronic System Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixed-signal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10X speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7% and 3%, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.