Variable domain transformation for linear PAC analysis of mixed-signal systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Symbolic modeling of periodically time-varying systems using harmonic transfer matrices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than --22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 µm digital CMOS process, the prototype PLL occupies an area of 0.18 µm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.