Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding

• Authors: Kedarnath J. Balakrishnan
• Venue: VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
• Year: 2007

An efficient LFSR reseeding based scan vector compression scheme is proposed in this paper. By using a two step scheme of multiple small LFSRs and dictionary encoding of the LFSR seeds, very high compression can be achieved on scan load patterns. The proposed scheme involves reseeding only the required LFSRs depending on the number of specified bits in a scan load pattern thereby improving the encoding efficiency. Experiment results show that very high encoding efficiency can be achieved using the proposed scheme. Multiple small LFSRs are advantageous to a dictionary based compression scheme of the LFSR seeds. An algorithm to choose seeds intelligently to achieve higher second level compression is described. The proposed scheme can be used in both full Built-In Self-Test (BIST) environments and Hybrid-BIST environments where the compressed data is stored on the external test equipment. Experiments show that the proposed scheme requires less tester memory as compared to previously published results.