Transient power supply current monitoring—a new test method for CMOS VLSI circuits
Journal of Electronic Testing: Theory and Applications
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
IDDT Testing versus IDDQ Testing
Journal of Electronic Testing: Theory and Applications
Experimental Results on BIC Sensors for Transient Current Testing
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Dynamic Power Supply Current Testing of CMOS SRAMs
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Fault Detection and Location Using IDD Waveform Analysis
IEEE Design & Test
Transient Power Supply Current Testing of Digital CMOS Circuits
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Digital Integrated Circuit Testing using Transient Signal Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATS '97 Proceedings of the 6th Asian Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed. This paper precisely defines the concept of average transient current (IDDT) of CMOS digital ICs, and experimentally analyzes the feasibility of IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions, which enables IDDT test generation at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation. Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5, and likely to be IDDT testable. It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test. IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by using IDDT testing.